This invention relates to the manufacture of semiconductor devices including MOS transistor components disposed along the side walls of trenches formed on an "upper" surface of a semiconductor chip.
For increasing the density of semiconductor device components per surface area of semiconductor chips, a recent practice has been to form narrow trenches on a surface of the chips and to dispose MOS transistor components in vertical orientation along the trench walls. Thus, while surface area of the chips is taken up by the trenches, the surface area lost to the trenches is more than made up by the surface areas of the vertical walls of the trenches.
A typical MOS transistor component (forming part of semiconductor devices such as insulated bipolar transistors, MOS controlled thyristors, and MOS transistors) comprises source and drain regions of the same conductivity type separated by a channel region of opposite type conductivity. Conduction of charge carriers from the source region to the drain region through the channel region is controlled by a voltage applied to a gate electrode overlying the channel region and separated therefrom by a thin layer of a dielectric material. With chips of silicon, the dielectric material is typically silicon dioxide.
In the manufacture of such trench devices, and particularly semiconductor devices used in power controlling applications, a starting workpiece comprises a silicon chip comprising an "underlying" substrate of relatively heavily doped silicon, e.g., of N type, an intermediate silicon layer interfacing with the substrate and, in this example, lightly doped N type, and an overlying silicon layer "moderately" doped, of P type. In the completed device, the intermediate layer and substrate comprise a drain region common to a plurality of MOS components (connected in parallel within a single or "discrete" power device), and the overlying layer comprises the channel region of each of the MOS components. Completion of the workpiece requires the addition of a source region, a gate oxide, and source and gate electrodes for each MOS component as well as a drain electrode for the common drain region. This is accomplished by first forming spaced apart regions of N type conductivity across the upper surface of the chip, e.g., by ion implantation. The N type regions extend only part way through the overlying P type layer and are to comprise the source regions of the MOS components. Significantly, because the spaced apart source regions are provided in a uniformly doped layer, i.e., without defined features, little precision is required in the process.
With the source regions in place, trenches are then etched entirely through the overlying P layer through each of the source regions. Great precision is required, but the previously formed source regions are clearly visible and provide a means for precise alignment of the photomask used in the trench etching process. With the trenches in place, thus exposing vertical surfaces which extend through the source regions, the underlying P type layer and a portion of the N type intermediate layer, the trench walls are coated, e.g., in a thermal oxidation process, with a layer of silicon dioxide. The trenches are then filled with an electrically conductive material, e.g., doped polycrystalline silicon, which serves as the gate electrode of the MOS components formed vertically along the trench walls. The silicon dioxide layers covering the trench walls serve as the gate electrode dielectric layer of the various MOS components as well as an insulator at the bottoms of the trenches for electrically isolating the gate electrodes from the underlying drain regions.
For completing all the MOS components, electrically conductive layers are provided on the chip surfaces serving as source and drain region electrodes and extensions of the gate electrodes.
Preferably, for high packing density of the MOS components on the chip, all the elements added to the initial chip workpiece are as small as possible, e.g., the trenches have the smallest widths achievable using known etching processes. Also, for desirable electrical characteristics, the gate oxide layers are uniformly thin. Two basic problems are found to exist with the known manufacturing processes. One is that the trench walls are not uniformly straight and smooth, and the second is that the gate oxide layers are not uniformly thick. The effect of such structural variations is variations in electrical characteristics of the various MOS components. Ideally, all the MOS components should have identical shapes and dimensions and identical electrical characteristics. The present invention is directed toward reducing the structural variations among the MOS components and improving the uniformity of the electrical characteristics thereof.